Archives

  • 2018-07
  • 2019-04
  • 2019-05
  • 2019-06
  • 2019-07
  • 2019-08
  • 2019-09
  • 2019-10
  • 2019-11
  • 2019-12
  • 2020-01
  • 2020-02
  • br Tests and measurements We used a set of

    2020-02-13


    Tests and measurements We used a set of FPGA cores for all tests and measurements. Firstly, the control circuit for the Controlled Current Limiter illustrates the proposed TMR method. The circuit contains a D-Register to enable or disable the power to the protected device, a counter, which is used to force the power during the initial transient period, and a couple of logic gates, which detect any over-current condition and switch the power off. The device can then be restarted by an external circuit. For this circuit, only the SENSE and POWER signals (the SENSE pin is the input, which signals an overcurrent condition and the ENABLE is the output which controls the state of the current limiter) are connected to I/Os and as such, care must be taken as to how to connect them inside the FPGA. The power pin should be connected to an output voter as presented in Fig. 10, while the SENSE input can be either connected directly or through the use of the circuit presented in Fig. 10. Other pins are internal and are connected to each separate instance. The clocks should be shifted and generated by a PLL with individually settable delays, while the reset lines should be synchronous to this clock. The START input itself is wired internally, so it YM 022 is separately connected to each instance (Fig. 16). For these FPGA core implementations, the logic utilization was analyzed for two different Flash-based FPGAs (the IGLOO2 family and the ProASIC3 family), contrasting the single implementations with the proposed TMR methods. It can be seen from the results presented in Table 3 that in addition to the 300% overhead taken by the triplication of the logic, the additional overhead imposed by the TMR methods is quite small – 7% and 5% of the single implementation respectively for the combinatorial logic elements, and 3% of the single implementation in both cases for the sequential logic elements. In order to evaluate the functionality of the proposed FDIR approach a test was performed under simulated conditions on all the types of current limiters together, including the Analog Watchdog. The parts used to implement the current limiter and watchdog timer can be seen in Table 4. We specifically chose parts that are inherently tolerant to SEE, to perform tests on hardware that could be used in a nanosatellite. Passive components, which are normally not susceptible to radiation, are not listed. The Power Distribution Current Limiter was used to power a load and the Autonomous Current Limiter, which in turn was used to power a load and the Controlled Current Limiter and its load. Everything was controlled by a single FPGA powered separately (due to the Power Distribution Current Limiter) and the watchdog was also evaluated alongside. The current consumption was simulated to be approximately 1A in total – 50mA load for the Controlled current limiter and 500mA loads for the other two current limiters. The output of each current limiter was then short-circuited to ground by a silicon diode, which mimics the effect of a SEL induced short-circuit event. The FPGA functionality was also disabled to evaluate the functionality of the external watchdog (Fig. 17). The graphs presented in Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25, Fig. 26 show the output voltages of the individual current limiting circuits (the upper plot (line 1) presents the output from the Power Distribution Current Limiter, the upper middle plot (line 2) presents the output from the Autonomous Current Limiter, the bottom middle plot (line 3) presents the output voltage of the Controlled Current Limiter and the bottom plot (line 4) presents the measured current of the relevant Current Limiter under test. It can be seen from the results of the functionality test, that the power distribution is handled hierarchically – the faults do not propagate up the chain. Additionally, the reaction time (the time that must pass for the power to be switched off after an overcurrent condition occurs) can be measured: the values are 3.66 us for the Controlled Current Limiter, 12 us for the Autonomous current limiter, 13.28ms for the Power Distribution Current Limiter with a first-order Delta-Sigma modulator and 1.46ms for the Power Distribution Current Limiter with a third-order Delta-Sigma modulator. Here Active site should be noted that the Power Distribution Current Limiter also limits the input current to a set value, which means that the relatively longer fault condition does not present an issue. Further, in certain Figures it can be seen that the fault conditions do cause voltage spikes that propagate up the hierarchy. The reason for this is that the tests were performed with low capacitances on each current limiter and load (a sort of worst case scenario). In practice this YM 022 would not occur, as larger bypass capacitors would be used as part of best practice design techniques. It can also be seen from Fig. 25 that if the FPGA ceases to trigger the Watchdog, its power is cycled, which restores functionality.